Generally, transistor active areas within a given semiconductor substrate surface area all have a uniform length, such that the surface area that comprises the active areas is rectangular with each active area's length being the length of the rectangular area. However, this patterning may result in higher corner stress in each active area and in higher stress in each active area and the shallow trench isolation (STI) adjoining the active area. For example, the oxide in the STI may cause a tensile stress in the STI and a compressive stress in the active area. Further, this patterning generally creates more difficulty in processing, particularly in etching. This may be because occasionally different spaces between adjacent active areas cause different loading effects and chemical reactions such that keeping the active areas uniform may be difficult.
These problems may become more pronounced as transistor sizes are further scaled down. The problems may be present in both planar field effect transistors and in fin field effect transistors (FinFETs), but may be more problematic in FinFETs. Accordingly, there is a need in the art to overcome these problems and disadvantages.